This invention generally relates to a display information processing apparatus and more particularly to a read/write display information processing apparatus suitable for fast reading/writing of display data with respect to a graphic memory and fast refreshing of display data on a display unit, the display data being representative of characters and graphics to be displayed on the display unit which uses, for example, a cathode ray tube (CRT) or liquid crystals for displaying the display data as in the case of word processors and personal computers or a printer for recording and displaying the display data.
In recent years, a display unit based on a bit map display scheme has been used widely for word processors and personal computers. This type of display unit employs, for the sake of displaying characters and graphics on the CRT or liquid-crystal screen, a graphic memory which has a large degree of freedom of display contents and a memory element of one bit corresponding to one bit of a display picture element or pixel.
The bit map display scheme is however disadvantageous in that display data for one display screen must be written bit by bit into the graphic memory, resulting in a low display speed and that when the display content is frequently refreshed, the load on a processor (hereinafter referred to as a CPU) is increased in order to perform the write processing, thus retarding processings for other modes of control.
Under the circumstances, a method has been proposed which is designed to speed up the processing for writing the display data into the graphic memory and to reduce the load applied on the CPU which is engaged in performing the write processing. A display system disclosed in JP-A-60-260989 corresponding to a Japanese Patent Application filed Jun. 8, 1984 by the inventor of the present application proposes reduction of the load on the CPU in the course of both the bit shift processing performed when writing write (refresh) data into the graphic memory and the combining processing of the write data and background data.
However, the above prior art display system fails to consider the way of accessing the memory for the sake of reading display data to be combined out of the graphic memory and writing the combined display data into the graphic memory, the way to reduce the amount of write data necessary for display refreshing and the way to efficiently utilize a memory area of the graphic memory which is not used as a display picture data memory area.
For example, in an apparatus in which the graphic memory is accessed on a time-share basis in order to prevent pictures from flickering when refreshing the screen, a graphic memory of a minimal 16-bit width structure is required to meet the screen which is, for example, of a raster of 1024 dots.times.512 dots. When a single graphic memory is constructed using four DRAM's each having a structure of 64 k bits.times.4 k bits, this graphic memory has a capacity of 128 k bytes. However, since the capacity of the display screen is 64 k bytes, a surplus 64 k byte memory area of the graphic memory is left unused as the display picture data memory area. Further, in the conventional display data processing, data for the entirety of the screen has to be revised when scrolling the screen, and in order to revised data which is bit-shifted beyond a word boundary when scrolling, the write processing must be carried out plural times to write the shifted data, resulting in a low processing speed.